The present invention relates to a method of wiring a power supply to large-scale integrated circuit and, more particularly, to a method of wiring a power supply for large-scale integrated circuit adapted so as to effectively design the wiring for the power supply for large-scale integration as a part of large-scale integration family, including a large-scale integrated circuit such as a gate array LSI, whose chip size (exterior dimension) varies with the scale or size of a logic circuit or a memory circuit to be formed in the large-scale integrated circuit.
Heretofore, in the technique of designing the wiring for a power supply for a large-scale integrated circuit such as designing the wiring for power supply for a gate array LSI of a fixed channel type, basic data such as width of the wire, its location, the number of wires, etc., is predetermined for each chip size, and the design for the wiring is performed by using such basic data. Hence, the wiring is predetermined in a fixed manner regardless of the scale or size of the power supply required for the effective operation of a function circuit, such as a logic circuit, a memory circuit, etc.
The technique of designing the wiring for a power supply so as to vary the width of the wire with consumption of electric power is disclosed, for example, in Japanese Patent Laid-open Publication (kokai) No. 173,855/1985. This technique involves constructing an integrated circuit so as to vary its wire width in approximate proportion with the magnitude of electrical power consumed by the logic and memory circuits.
It is to be noted that, for a LSI composed of logic and memory CMOS (Complementary Metal Oxide Semiconductor) circuit serving as a function device constituting the integrated circuit, its operative frequency serves as a parameter indicative of the magnitude of electric power consumed. Hence, in this case, the integrated circuit is so designed as to vary the width of wire with its operative frequency.
It should be noted, however, that the consumption of electric power by the large-scale integrated circuit varies with the scale or size of the function circuits such as logic circuits or memory circuits to be formed in the large-scale integrated circuit and with the operative frequency, so that the technique of wiring for the power supply to the integrated circuit as described hereinabove requires the wiring to change in accordance with the consumption of electrical power. This means that, in preparing CMOS gate array LSIs as a large-scale integration family, the technique of designing the specification for optimum wiring with its use taken into account becomes complex because the chip size should be changed in accordance with the size or scale of integration.
Further, the prior art method for wiring a power supply as described hereinabove requires the wiring to be performed with a surplus of electrical characteristics required for wiring for the power supply because nothing about the scale of the logic circuits and the memory circuits during the effective operation is taken into account in setting the wiring for the power supply to the gate array LSIs. Hence, a surplus of wire is generally provided.
When the wiring is performed through automatic designing by computer processing, the operation of the logic circuit at each location should be simulated in order to set the width of the wire on the basis of the operative frequency of the logic circuit. Consequently the conversion an algorithm for automatic designing becomes difficult.